This application claims the benefit of the Korean Application No. P2002-63678 filed on Oct. 18, 2002, which is hereby incorporated by reference.
1. Field of the Invention
The present invention relates to a circuit for correcting a duty factor of a clock signal, and more particularly, a circuit for correcting a duty factor of a clock signal by using a two delay loops.
2. Background of the Related Art
In general, when an application circuit, such as a VLSI (Very Large Scale Integration), is operative in response to a clock signal, there is a case when a clock signal provided to the application circuit is involved in failure in sustaining a 50% duty factor exactly, but variation of the duty factor.
The duty, factor is a value a high state time period of the clock signal is divided by a cyclic period of the clock signal. If the duty factor fails to be sustained at 50% exactly, the application circuit operative at a rising edge and a falling edge of the clock signal malfunctions. Therefore, it is required that the duty factor is corrected so to be 50%, exactly.
There are many known circuits for correcting the duty factor to be 50%. However, most of the circuits are analogous, with a complicate system and difficulty in fabrication. Moreover, there is a difficulty in designing a tailor made correcting circuit for every application circuit.
Accordingly, the present invention is directed to a circuit for correcting a duty factor of a clock signal that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a circuit for correcting a duty factor of a clock signal, for correcting a duty factor of a clock signal to be 50%, exactly.
Another object of the present invention is to provide a circuit for correcting a duty factor of a clock signal, which has a simple system, and is easy to fabricate.
Further object of the present invention is to provide a circuit for correcting a duty factor of a clock signal, which is applicable to any kind of application circuit, easily.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these objects and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described herein, the circuit for correcting a duty factor of a clock signal, includes a phase comparator for detecting a phase difference of an input clock signal having a duty factor to be corrected, and a corrected clock signal having the duty factor corrected, and generating a shift control signal, a control signal generating part for shifting a clock generating reference signal in response to the shift control signal, and delaying the clock generating reference signal for a preset time period to generate 180xc2x0 and 360xc2x0 clock generating control signals, and a clock signal generating part for generating a clock signal having a corrected duty factor according to the 180xc2x0 and 360xc2x0 clock generating control signals.
The control signal generating part includes a shift register for shifting the clock generating reference signal in a left/right direction in response to a shift control signal, a synchronized signal providing part for synchronizing a shifted clock generating reference signal to the input clock signal, a first delay loop for delaying the synchronized clock generating reference signal for a preset time period, to provide as a 180xc2x0 clock generating phase signal, and a second delay loop for delaying the synchronized clock generating reference signal for a preset time period, to provide as a 360xc2x0 clock generating phase signal.
The shift register stores a high voltage as the clock generating reference signal, and shifts the clock generating reference signal, the first delay loop delays the clock generating reference signal for a preset time period set according to a shifted position of the clock generating reference signal, and the second delay loop delays the clock generating reference signal for a time period two times longer than a delay time period delayed by the first delay loop.
The first or second loop includes a plurality of delays disposed between output terminals of the synchronized signal providing part.
The clock signal generating part includes a correction delay for delaying the 360xc2x0 clock generating control signal, a first pulse signal generator for generating a pulse signal in response to the 360xc2x0 clock generating control signal delayed at the correction delay, a second pulse signal generator for generating a pulse signal in response to the 180xc2x0 clock generating control signal, and a corrected clock signal generator for generating clock signals respectively having 360xc2x0 and 180xc2x0 phases in response to the pulse signals from the first pulse signal generator and the second pulse signal generator.
The correction delay delays a time period required from a time the first and second pulse signal generators generate pulse signals to a time the clock signal generating part generates clock signals having 360xc2x0 and 180xc2x0 in response to the generated pulse signals.
The first or second pulse signal generator includes a first inverter group for delaying and inverting an output signal from the correction delay or the 180xc2x0 clock generating control signal from the control signal generating part, an NAND gate having a first terminal for receiving the output signal from the correction delay or the 180xc2x0 clock generating control signal from the control signal generating part and a second terminal for receiving an output signal from the first inverter group, and a second inverter group for delaying and inverting an output signal from the NAND gate.
The first inverter group includes three inverters connected in series, and the second inverter group includes one inverter.
The corrected clock signal generator includes first and second transistors connected between power terminal Vdd and a ground in series, for receiving an output signal from the first and second pulse signal generators, and a plurality of inverters connected between the first and the second transistors.
The first transistor is a PMOS transistor, and the second transistor is an NMOS transistor, and the first transistor has a gate connected to an inverter for receiving an inverted output signal of the first pulse signal generator, and the second transistor has a gate connected to receive the output signal of the second pulse signal generator.
The plurality of inverters are first, second and third inverters, wherein the first and second inverters are connected in parallel to serve as a latch, and the third inverter is connected in series to the first or second inverter.
It is to be understood that both the foregoing description and the following detailed description of the present invention are exemplary and explanatory and are intended to provide further explanation of the invention claimed.